1. Field of the Invention
The present invention relates to a transmitting apparatus that generates bit sequences so as to tend to equalize error tolerance among blocks of data that are transmitted.
2. Description of the Related Art
Standardization is now under development for the W-CDMA system which is a system of the 3rd generation mobile communication systems of the 3rd generation Partnership Project (3GPP). As a theme of the standardization, the High Speed Downlink Packet Access (HSDPA), which can provide a maximum transmission rate of about 14 Mbps in the downlink, is specified. The HSDPA employs an adaptive coding modulation scheme and is characterized, for example, in that the QPSK modulation scheme and the 16 QAM scheme are adaptively switched in accordance with the radio transmission environment between the base stations and mobile stations. Moreover, the HSDPA also employs the Hybrid Automatic Repeat request (H-ARQ) scheme in which if an error is detected in the data transmitted from a base station, re-transmission is executed responding to a request from a mobile station.
The main radio channels used for the HSDPA include the High Speed-Shared Control Channel (HS-SCCH), the High Speed-Physical Downlink Shared Channel (HS-PDSCH), and the High Speed-Dedicated Physical Control Channel (HS-DPCCH).
The HS-SCCH and HS-PDSCH are both shared channels for a downlink (namely, in the direction from the base station to the mobile station), while HS-SCCH is the control channel for transmitting various parameters in regard to the data transmitted by the HS-PDSCH. Among the parameters, information such as the modulation type, which indicates the modulation scheme used for transmission of the data with HS-PDSCH, and the number of assignments (number of codes) of the spread code, may be listed.
Meanwhile, the HS-DPCCH is an dedicated control channel for the uplink (namely, in the direction from the mobile station to the base station) and is used when the mobile station transmits the ACK and NACK signals to the base station in accordance with acknowledgment and no-acknowledgement of reception of data received via the HS-PDSCH.
Moreover, the HS-DPCCH is also used for transmitting the result of the measurement of the reception quality (for example, the signal to interference ratio (SIR)) to the base station as the Channel Quality Indicator (CQI). The base station judges quality of radio environment of the downlink based on the received CQI. When the environment is not good, a modulation scheme which is capable of transmitting the data at a higher transmission rate is selected. When the environment is good, a modulation scheme which is capable of transmitting the data at a lower transmission rate is selected (namely, adaptive modulation is executed).
Channel Format
Next, a channel format in the HSDPA will be described.
FIG. 1 is a diagram illustrating a channel format in the HSDPA. Since W-CDMA employs the code division multiplexing system, each channel is separated with the spreading codes.
First, the channels not described above will be described briefly.
Common Pilot Channel (CPICH) and Primary Common Control Physical Channel (P-CCPCH) are respectively common channels for the downlink.
The CPICH is used for estimation of channel condition and cell search in the mobile station and as the timing reference for the other physical channel for downlink in the same cell. In other words, this CPICH is the channel for transmitting the pilot signal. The P-CCPCH is the channel for transmitting the broadcast information to the mobile stations.
Next, timing relationship of channels will be described with reference to FIG. 1.
As illustrated in the figure, each channel forms one frame (10 ms) with 15 slots. As described previously, since the CPICH is used as the reference of the other channel, the top of frames the P-CCPCH and HS-SCCH are matched with the top of frame of the CPICH. Here, the top of frame of the HS-PDSCH is delayed by two slots from the HS-SCCH or the like in order to execute the demodulation of the HS-PDSCH with the demodulation method corresponding to the received modulation type after the mobile station has received the modulation type information via the HS-SCCH. Moreover, the HS-SCCH and HS-PDSCH form one sub-frame with three slots.
The HS-DPCCH is used as the uplink channel, although not synchronized with the CPICH, on the basis of the timing generated by the mobile station.
The channel format of the HSDPA has been described above briefly. Next, the process up to transmission of the transmission data via the HS-PDSCH will then be described with reference to the block diagram.
Structure of Base Station
FIG. 2 illustrates a structure of a base station supporting the HSDPA.
In FIG. 2, the reference numeral 1 designates a CRC attachment unit; 2, a code block segmentation unit; 3, a channel coding unit; 4, a bit separating unit; 5, a rate matching unit; 6, a bit collecting unit; and 7, a modulation unit.
Next, operations of each unit will be described.
The transmission data transmitted via the HS-PDSCH (data stored in one sub-frame of the HS-PDSCH in FIG. 1) is first subjected to the CRC arithmetic process in the CRC attachment unit. Accordingly, the result of the arithmetic operations is attached to the last portion of the transmission data. The transmission data to which the result of CRC arithmetic operation is attached is then input to the code block segmentation unit 2 and is then segmented into a plurality of blocks. This segmentation is executed to shorten the unit data length for the error correcting coding, considering the load of decoding process on the receiving side. When the length of data has exceeded the predetermined length, the data is equally segmented into a plurality of blocks. An integer 2 or larger is selected as the number of segmentations and, as an example, the processes when the number of segmentations is 2 will be described here.
The segmented transmission data are respectively processed as the object data of individual error correcting coding processes in the channel coding unit 3. Namely, the error correcting coding process is executed respectively to the segmented first block and second block. As an example of the channel coding, turbo coding is considered.
Here, the turbo coding system will be described briefly. In the turbo coding system, when the object data of the coding is defined as U, the data U itself, the data U′ obtained by the convolutional coding of the data U and the data U″ obtained by executing the interleaving on the data U and then executing the convolutional coding on the interleaved data are outputted. Here, U is called the systematic bits and are the data used in both element decoders for the turbo decoding. This data U can be understood as the data having higher importance because of higher application frequency. On the other hand, U′ and U″ are called the redundant bits and are used only one of two element decoders. These data can be understood as having a degree of importance which is lower than the data U because of lower application frequency.
Namely, it can be said that the systematic bits have a degree of importance which is higher than that of the redundant bits and a correct decoding result can be obtained with the turbo decoder if the systematic bits are received more correctly.
The systematic bits and redundant bits generated as described above are inputted as the serial data to the bit separating unit 4. The bit separating unit 4 separates the input serial data into the data U, U′ and U″ of three systems and then outputs these data as parallel data.
The rate matching unit 5 executes the puncturing process for deleting the bits and also executes the repetition process by repeating the bits with the predetermined algorithm in order to store the data into a sub-frame formed of three slots of the HS-PDSCH.
The bits having completed the bit adaptation process to the sub-frame in the rate matching unit 5 are then input in parallel to the bit collecting unit 6.
The bit collecting unit 6 generates and outputs, on the basis of the input data, bit sequences of 4 bits indicating each signal point, for example, of the 16 QAM modulation.
The modulating unit 7 outputs the signal modulated by the 16 QAM modulating method in the amplitude and phase corresponding to the signal point indicated by the input bit sequence and then sends the signal to the antenna (not illustrated) after conversion into a radio frequency signal through frequency conversion.
Arrangement Method
Here, the processes in the bit collecting unit will be described in further detail.
FIG. 3 illustrates the arrangement method in the bit collecting unit 6.
The bits including the systematic bits, redundant bits or the like output through the rate matching process are required to correspond to the bit sequences indicating the signal points in the 16 QAM modulation. Therefore, these data must be arranged in the units of 4 bits.
The systematic bits and redundant bits are segmented, by the code block segmentation unit, into two groups, the first block, and the second block. However, since these bits are stored in the same sub-frame, the bits are coupled again into one aggregation and processed as one data block in the bit collecting unit 6.
In FIG. 3, the bit sequences as a whole indicated as Nr(4)×Nc (10) corresponds to the coupled systematic bits and redundant bits. The regions indicated as S1, S2, S3 and P2-1 of the first column are bit sequences corresponding to one signal point for the 16 QAM modulation. According to FIG. 3, since 10 bit sequences are provided, a 10 bit sequence expresses 10 signal points because 1 bit sequence expresses 1 signal point.
Next, a bit alignment procedure will be described.
First, in the code block segmentation unit 2, the total number of systematic bits Nsys of each block of two segmented blocks(the sum of the number of the first systematic bits and the number of the second systematic bits after the rate matching process) is obtained.
Next, a quotient A and a remainder B are obtained by dividing Nsys with the total number of columns Nc (total number of bits 40÷number of bit sequences 4=10).
The number of rows, which is equal to the quotient A obtained, are defined sequentially from the top as the regions for systematic bits. Moreover, the regions in the left side of the rows of the regions occupied by the systematic bits are sequentially defined, as many as the same number as the remainder B, as the regions for systematic bits.
According to this definition, the regions indicated in FIG. 3 with the oblique lines are defined as the regions for systematic bits. The remaining regions are defined as the regions for redundant (parity) bits.
Next, the systematic bits of the first block are sequentially assigned to the region defined for the systematic bits toward the bottom in the column direction from the first line, first column. When the systematic bits region of the first column are filled, the systematic bits of the second column are filled in the same manner.
Meanwhile, the redundant bits are sequentially assigned from the first column to the region for the redundant bits illustrated in FIG. 3. In particular, the redundant bits corresponding to U′ are defined as the first redundant bits, while the redundant bits corresponding to U″ are defined as the second redundant bits, the first bit of the second redundant bits of the first block is assigned to the first column of the redundant bits region, the first bit of the first redundant bits of the first block is assigned to the second column of the redundant bits region, and the second bit of the second redundant bits of the first block is assigned to the third column. As described above, the redundant bits regions are assigned by alternately assigning the second redundant bits and first redundant bits. In FIG. 3, the arrow marks indicate the arrangement sequence and PM-N indicates that N-th bit of the M-th redundant bits must be arranged.
The bit columns, namely bit sequences, arranged as described above, indicate the signal points on the phase plane illustrated in FIG. 4. For example, the bit column indicates the signal point A when (S1, S2, S3, P2-1)=(1, 0, 1, 1).
Such an arrangement method is disclosed, for example, in the following document:                3G TS 25. 213 (3rd Generation Partnership Project: Technical Specification on Group Radio Access Network; Spreading and modulation (FDD))        
There are a number of problems to be found in the prior art described above.
Namely, when the mapping on the phase plane as described above is executed while multi-level modulation is introduced, the lower bits (S3, S6, S9, . . . , P2-7, P2-8, P2-1, P1-1, . . . , P1-7, P1-8) are in the trend, against the upper bits, (S1, S4, S7, . . . , S21, S23, S2, S5, S8, . . . , S22, S24) of each aligned bit column, to easily generate an error during determination of the signal point on the receiving side due to variation of phase and amplitude in the radio transmission. However, as illustrated in FIG. 3, when the segmented first block is compared with the second block, the four systematic bits of the first block are arranged in the lower bits, while none of the systematic bits of the second block are assigned to the lower bits.
As described previously, the systematic bits can be understood as the important pieces of information. According to the arrangement method described above, however, tolerance to phase and amplitude variations during radio transmission is different among the blocks due to the arrangement of the systematic bits.
Moreover, when the number of systematic bits is rather small, when the segmented first block is compared with the second block as illustrated in FIG. 8, the redundant bits of the first block are not assigned to the upper bits. However, the four redundant bits of the second block are assigned to the upper bits. According to the arrangement method also as described above, tolerance to phase and amplitude variations during radio transmission is different among the blocks due to the arrangement of redundant bits.
Accordingly, there arise problems in that a difference in tolerance is generated among the blocks resulting from arrangement of signal points even when the same kind of bits are used in the blocks in any case of systematic bits and redundant bits, and moreover reception quality itself is also different in accordance with the block used, creating a difference in quality among the blocks.
An object of the present invention is to provide equalization of tolerance to an error among the blocks.
Moreover, there exists the problem that when an error correction process in the turbo coding process is to be executed, a block having higher tolerance has a margin of error correction that handles the occurrence of further error, but a block having lower tolerance likely falls into the situation in which an error is generated that exceeds the error correction capability, and therefore such a condition is not effective.
Another object of the present invention is to enhance the efficiency of error correction by equalizing the tolerance to error in the blocks when an error correction process, such as turbo coding, is to be executed.
Moreover, another object of the present invention is to reduce the case of transmitting unnecessary signals, by increasing likelihood of simultaneous generation of error in both blocks and that of no generation of error in either block. Such as system may re-transmit the block not generating an error because the system that cannot identify the block generating an error among a plurality of blocks is employed.
In addition, it can also be considered as one of the objects of the present invention to provide the effect which can be attained from each structure of the preferred embodiments thereof described later and which cannot be obtained with the prior art.